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Journal of Logic and Computation Advance Access published online on February 26, 2009
Journal of Logic and Computation, doi:10.1093/logcom/exn075
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© The Author, 2009. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oxfordjournals.org

Original Papers

Comparing LTL Semantics for Runtime Verification

Andreas Bauer

Computer Sciences Laboratory, Australian National University, Canberra, Australia.
E-mail: baueran{at}rsise.anu.edu.au

Martin Leucker

Institut für Informatik, Technische Universität München, München, Germany.
E-mail: leucker{at}in.tum.de

Christian Schallhart

Fachbereich Informatik, Technische Universität Darmstadt, Darmstadt, Germany.
E-mail: schallhart{at}forsyte.de

Received 7 June 2008.


  Abstract

When monitoring a system w.r.t. a property defined in a temporal logic such as LTL, a major concern is to settle with an adequate interpretation of observable system events; that is, models of temporal logic formulae are usually infinite words of events, whereas at runtime only finite but incrementally expanding prefixes are available.

In this work, we review LTL-derived logics for finite traces from a runtime-verification perspective. In doing so, we establish four maxims to be satisfied by any LTL-derived logic aimed at runtime verification. As no pre-existing logic readily satisfies all of them, we introduce a new four-valued logic Runtime Verification Linear Temporal Logic RV-LTL in accordance to these maxims. The semantics of Runtime Verification Linear Temporal Logic (RV-LTL) indicates whether a finite word describes a system behaviour which either (i) satisfies the monitored property, (ii) violates the property, (iii) will presumably violate the property, or (iv) will presumably conform to the property in the future, once the system has stabilized. Notably, (i) and (ii) correspond to the classical semantics of LTL, whereas (iii) and (iv) are chosen whenever an observed system behaviour has not yet lead to a violation or acceptance of the monitored property.

Moreover, we present a monitor construction for RV-LTL properties in terms of Moore machines signalizing the semantics of the so far obtained execution trace w.r.t. the monitored property.

Keywords: Runtime verification; temporal logic; monitoring


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